Product Summary

The XPC860SRZP66D4 is a Quad Integrated Communications Controller. The device is designed for a variety of controller applications. It particularly excels in both communications and networking systems. The CPU on the XPC860SRZP66D4 is a 32-bit MPC8xx core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowePC instruction set. The communications processor module (CPM) from the XPC860SRZP66D4 QUICC has been enhanced by the addition of the inter-integrated controller (I2C) channel. The memory controller has been enhanced, enabling the MPC860 to support any type of memory, including high-performance memories and new types of DRAMs.

Parametrics

XPC860SRZP66D4 absolute maximum ratings: (1)Supply Voltage, VDDH: –0.3 to 4.0 V; VDDL: –0.3 to 4.0 V; KAPWR: –0.3 to 4.0 V; VDDSYN: –0.3 to 4.0 V; (2)Input Voltage, Vin: GND – 0.3 to VDDH V; (3)Temperature, TA(min): 0 ℃; Tj(max): 95 ℃; (4)Temperature (Extended), TA(min): –40 ℃; Tj(max): 95 ℃; (5)Storage Temperature Range, Tstg: –55 to 150℃.

Features

XPC860SRZP66D4 features: (1)Instruction and data caches are two-way, set-associative, physically addressed, LRU replacement, and lockable on-line granularity; (2)MMUs with 32-entry TLB, fully associative instruction, and data TLBs; (3)MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups; (4)Advanced on-chip-emulation debug mode; (5)Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits); (6)32 address lines; (7)Operates at up to 80 MHz; (8)Four 16-bit timers or two 32-bit timers; (9)Gate mode can enable/disable counting; (10)Interrupt can be masked on reference match and event capture.

Diagrams

XPC860SRZP66D4 External Clock Timing

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